Evaluating Coarse-Grained FPGAs having Hard Blocks Placed in Columns

Abstract

This work uses a coarse-grained FPGA architecture exploration environment to compare a column-based FPGA architecture with a non-column based architecture. Different groups of netlists are collected and a single floor-planning is optimized for all the netlists in a group. It has been found that the coarse-grained architectures that do not limit their hard-blocks to columns give much better placement costs and routing channel usage than the architectures that limit their hard-blocks to columns. Though a column based architecture can give a more compact layout as compared to a noncolumn based architecture; but the latter gives higher gains in the channel width requirements and can result in overall area gain.